`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/08/03 19:55:24
// Design Name: 
// Module Name: MultiBankBram
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module MultiBankBram
#(
    parameter BANK=4,
    parameter DATA_WIDTH = 32,
    parameter ADDR_WIDTH = 32,
    parameter DEPTH = 1024
)
(
input logic clk,
input logic rst,
//write
input logic we [0:BANK-1],
input logic [ADDR_WIDTH-1:0] wr_addr [0:BANK-1],
input logic [DATA_WIDTH-1:0] wr_data [0:BANK-1],
//read
input logic [ADDR_WIDTH-1:0] rd_addr [0:BANK-1],
output logic [DATA_WIDTH-1:0] rd_data [0:BANK-1]
    );


genvar i;
generate
    for(i=0; i<BANK; i++)
    begin: bram_inst
        BlockRAM 
        #(.ADDR_WIDTH(ADDR_WIDTH),
          .DATA_WIDTH(DATA_WIDTH),
          .DEPTH(DEPTH))
        U (
        .clk(clk),
        .rst(rst),
        //read port
        .rd_addr(rd_addr[i]),
        .rd_data(rd_data[i]),
        //write port
        .we(we[i]),
        .wr_addr(wr_addr[i]),
        .wr_data(wr_data[i])
        );
    end
endgenerate

endmodule
